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FPGA & Matlab & Digital Signal Processing development

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  • 25.06.2024
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Kurzvorstellung

About 20 years of FPGA and Matlab/Simulink development.

Qualifikationen

  • FPGA5 J.
  • Simulink4 J.

Projekt‐ & Berufserfahrung

FPGA developer
Kundenname anonymisiert, Boeblingen
6/2021 – 7/2023 (2 Jahre, 2 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

6/2021 – 7/2023

Tätigkeitsbeschreibung

FPGA development.

Eingesetzte Qualifikationen

Digitaler Signalprozessor (DSP), FPGA, Simulink, Signalverarbeitung

FPGA developer
Kundenname anonymisiert, Bayern
3/2016 – 6/2021 (5 Jahre, 4 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

3/2016 – 6/2021

Tätigkeitsbeschreibung

FPGA development.

Eingesetzte Qualifikationen

FPGA, Signalverarbeitung, Videotechnik

FPGA designer
Kundenname anonymisiert, Mannheim
7/2013 – 2/2016 (2 Jahre, 8 Monate)
Military/Defense
Tätigkeitszeitraum

7/2013 – 2/2016

Tätigkeitsbeschreibung

FPGA projects for military and civil aviation.
FPGA designer/developer, HW/SW integrations, FPGA verification, troubleshooting of the most complex issues

Eingesetzte Qualifikationen

Embedded Entwicklung / hardwarenahe Entwicklung, Embedded Systems, Simulink

FPGA and DSP designer/developer
Kundenname anonymisiert, Stuttgart
1/2012 – 4/2013 (1 Jahr, 4 Monate)
Telekommunikation
Tätigkeitszeitraum

1/2012 – 4/2013

Tätigkeitsbeschreibung

- Development of 2G (GSM), 3G (UMTS), 4G (LTE) DSP processing chains and Viterbi, physical layer 1 (PHY1) on FPGA.
- Strong focus on functional and performance improvements of digital signal processing with significant decrease of FPGA resources (FlipFlops-FFs, DSP48E, BRAMs, logic, FIR Compilers,...) and high timing improvements for reaching the final timing closure.
- Implementation of new DSP processing modules on FPGA devices.
- System Generator (SysGen), CoreGen, FPGA editor.
- Absolute control of SysGen: one of many examples is implementation of dedicated scripts for compilation and timing analysis of multiple runs similar to SmartExplorer in Xilinx ISE. BlackBox usage for solving special cases like different memory primitives of BRAMs.
- Debugging timing reports to achieve timing closure. Generation of clear and easy understandable suggestions for improvements both in SysGen and VHDL code.
- Application of manual timing constraints in SysGen based on properties of signal processing.
- Specific individual view on timing closure in FPGA, improvements and figures of merit.
- Complex Matlab simulations both in float and fixed point of wireless signals at different sampling rates.
- Implemented AGC functionality for 3G Rx, based on exp/log functions.
- Design of absolutely optimal multistage multi-rate filters, with multiple iterations in Matlab and CoreGen.
- Half band, CIC, FIR, IIR, multiplier less filters. Mix of innovative and well-known DSP solutions. Advanced filter design.
- Multichannel (hardware folding) and time multiplexing of FPGA resources.
- Mentor’s ModelSim simulations.
- Documentation provided on the implemented modules and on new tool development.

Eingesetzte Qualifikationen

Embedded Entwicklung / hardwarenahe Entwicklung, Simulink, Embedded Software

Weitere Projekt‐ & Berufserfahrung anzeigen

Ausbildung

Ph.D. Degree - Doctorate in Electronics Engineering
Dr.-Ing
2011
Ljubljana, Slowenien
Master of Science in Electronics - 2.5 years
M.Sc.E.E.
2005
Belgrade, Serbien
University Electronics Engineer - 5 years
B.Sc.E.E.
1996
Belgrade, Serbien

Über mich

I simply deliver on time. Great troubleshooting and problem solving capabilities. Dedicated and committed person. Responsible. Hard working. Expressed combative spirit. Excellent communication and presentation skills. Focus on issues that have the highest impact on the team’s performance.

Weitere Kenntnisse

+ FPGA programming in VHDL and Verilog. High speed and high-performance FPGA designs (above 500 MHz). Parallel processing in GHz range on FPGA.
+ Xilinx devices: Ultra Scale+, Ultra-Scale, RFSOC, Kintex 7, Zynq, Spartan, Virtex 5&4&II-pro.
+ DO-254 FPGA design & development. DAL-A to DAL-C projects.
+ FPGA Verification per DO-254
+ PCIe for FPGA design.
+ AXI4 (AXI-bus) interfaces: Stream, Lite, Full.
+ Video processing FPGA based SD, HD, analog/digital input/output video streams. Implemented video processing algorithms, including frame-based and line/pixel streaming based algorithms.
+ UVVM based FPGA test-benches and verification.
+ Development of modules for advanced state-of-the-art instruments.
+ Digital Signal Processing (DSP) on FPGAs in GHz range, Xilinx RFSOC devices. Parallel signal processing with sampling rates above 60GHz.
+ BLDC motor control.
+ Audio processing (FPGA&IC based).
+ Complex glue logic for many ICs (FPGA based).
+ General and proprietary military interfaces: MilBus-1553, Arinc-429, CAN, SPI, I2C, UART, Arinc-818.
+ SDR (Software Defined Radio) in wireless 2G (GSM), 3G(UMTS), 4G(LTE) and for particle accelerators. Wireless Digital Signal Processing.
+ Memory interfaces DDR.
+ Matlab/Simulink. Generation of algorithms using Matlab script, different toolboxes and Simulink.
+ Expert on usage of Xilinx’s Matlab toolbox System Generator.
+ Successfully developed different instruments for synchrotron light sources (particle accelerators), the world’s most advanced scientific and research facilities.
+ Filtering: FIR, IIR, Half-Band, CIC, multiplier-less structures, lattice. Multi rate filters, polyphase filters.
+ AGC – Automatic Gain Control. Exp/log AGC function, and other implementations. Implemented in 3G Rx, accelerator instruments, V.34 modems.
+ Adaptive filtering: LMS (Least Mean Square), NLMS (Normalized LMS), RMS (Recursive Least Squares). System identification, noise and echo cancellation, complex equalizers.
+ Numerous modulators/demodulators: W-CDMA, OFDM, QAM, PSK (DPSK), DTMF, FSK, FM, PM, AM, Trellis-Coded (TCM).
+ Multi rate processing, multi stage multirate systems (decimation and interpolation including rational factors).
+ Digital Pre-Distortion – DPD for wireless systems.
+ FFT. Spectrum analysis.
+ Both time and frequency domain signal processing.
+ VHDL, Verilog HDL and SytemVerilog.
+ Xilinx Vivado & ISE tools. FPGA Editor, CoreGen, Constraints Editor, System Generator, Timing Analysis (STA – Static Timing Analysis), ChipScope, Impact.
+ Sigasi Studio.
+ Microsemi FPGA tools (Libero, Synplify)
+ Matlab and Simulink. Matlab toolboxes: Communication, DSP System, Fixed Point, Signal Processing, Filter Design, Link for Code Composer Studio, Simulink Real-Time Workshop, Xilinx System Generator. Matlab GUIs.

Persönliche Daten

Sprache
  • Serbisch (Muttersprache)
  • Kroatisch (Muttersprache)
  • Englisch (Fließend)
  • Slowenisch (Fließend)
  • Deutsch (Gut)
Reisebereitschaft
DACH-Region
Arbeitserlaubnis
  • Europäische Union
Profilaufrufe
2303
Alter
53
Berufserfahrung
28 Jahre und 1 Monat (seit 10/1996)
Projektleitung
5 Jahre

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