Harsha_curriculum_vitae

4/2013 – 9/2013

Design and Verification of Button Control, GPIO and Single/Two finger reset.

8/2012 – 1/2013

Design of Analog Control Module : FPGA, VHDL , Test and Validation on Board.

12/2009 – 4/2012

Design of RRH module for GSM network
Involved in development of upload and download transmission path for RRH system which involved mapping of GSM frame to CPRI line rate of 2.5GHz and mapping the data to different RF paths.

Partial Reconfiguration of FPGA
Partial reconfiguration is a design process that allows a limited, predefined portion of an FPGA to be partitioned and reconfigured while the remainder of the device continues to operate.

Verification of CPRI for 2.5GHz and 4.5Ghz
Involved in implementation of CPRI on Virtex 6 device and test its reliability with cascaded architecture having minimum round-trip delay.

Implementation of ADC and DAC interface for High-speed DDR data
Configuring ADC (ADS62P49) and DAC (DAC5688) to meet the new requirements of high speed DDR interface. Calibrating the FPGA using ODDR, IDDR, IDELAYCTRL and IODELAYE1 primitive elements to meet the requirement and have a reliable eye opening for efficiency.