Expert Embedded Systems and Automotive SW

8/2014 – 1/2018

VALEO Automotive R&D
Title: Senior Embedded Software Engineer
Cairo, Egypt.

Projects:

1. BMW iCAM3 RFK Camera System
Title: Senior Embedded Software Engineer / Tech Lead
Cairo, Egypt
Main Activities:
Responsibility over the overall SW architecture and design.
Training and technical guidance for 2 junior engineers in their ramp-up phase.
Analysis and discussions of BMW requirements with system engineers to commit on SW responsibility.
Review of the initial SW SRS requirements written by the team.
Monitoring, planning, reporting to Valeo BMW operations manager.

2. BAIC Surrounding View Camera System
Title: Senior Embedded Software Engineer
Cairo, Egypt
Main Activities:
Designed and implemented BLE (Bootloader Extension) to communicate with TI VisionMid A8 core for flashing slave DSP through SPI lines. BLE is being used in production line to flash the ECUs out for customer. This activity included:
Reverse engineering and code tracing of legacy black box Bootloader, to identify the required interface points between BL which handles CAN, and BLE which handles SPI.
Designing a generic BLE for slave core flashing.
Implementing a retry mechanism for failed SPI data chunks.
Implementing a CRC verification mechanism to ensure successful flashing on slave core side.
Writing generic, re-usable clean code for BLE SW Module, complying with MISRA C rules, ensured by PC-Lint static analysis tool.
Debugging through low level MCU peripherals; Flash Memory Module, SPI Module, CPU Clock Oscillator.
The newly used BLE contributed significantly to minimizing project costs for COTS (Components-Off-The-Shelf).
Handled full communication and technical agreements with the Bootloader supplier as below:
Presented the Application team and have been the interface point between the two teams.
Provided design for shared memory area between BL and Application.
 Led the agreements with BL supplier regarding the diagnostics transition techniques between the two SW parts.
Full ownership over external watchdog refreshment mechanism and dynamic handling between BL and Application.
Bug reporting, tracking and on-site support.
Designed and implemented an in-house Scheduler Manager BSW Package. The Scheduler Manager was developed to save costs and replace an existing commercial Operating System. This activity included:
Reverse engineering and tracing through an existing AUTOSAR OS to understand the OS behavior, and replace such behavior with the new SchM package.
Removal of OS from the SW through the AUTOSAR configuration tool.
De-coupling SW modules and tasks from the OS.
Removal of the OS from the SW build system.
Designing and implementation of MCU start-up code in Assembly.
Designing and implementation of system Linker Script, and ROM/RAM distribution between SW modules.
Handling system stack memory area.
Implementation of MCU Core Exception Table, and Interrupt Vector Table.
Writing low level HW drivers for the below peripherals:
MCU Interrupt Controller.
MCU STM Timer, with 5 ms tick time.
Designing, implementing, and maintaining a non-preemptive Scheduler Manager to drive the SW modules, with strict compliance to the following specifications:
Rate-Monotonic Scheduling technique.
Very light scheduling processing overhead.
Small ROM and RAM memory footprint.
Simple 3-state automata state machine.
Generic clean coding for re-usability.
MISRA C compliance through PC-Lint Tool.
Supporting the integration testing team to spot any possible bug in the new SchM package.
Providing complete analysis and profiling of each system task execution time, deadline, periodicity and CPU load.
Balancing and re-distribution of system tasks to lower down overall CPU Load from originally 80% to finally reach 32%.
Responsible for ASPICE pre-assessment of the project in the following areas:
SWE1: Software Requirements Analysis
SWE2: Software Architectural Design
SUP8: Configuration Management
Presented the team in the pre-assessment meetings, along with the project leader and team leader.
Debugging via Lauterbach Trace32 Debugger for PowerPC.
Creation of High level design objects/requirements, specification of interaction sequences, component interfaces, state machines, and UML dynamic behavior diagrams using Enterprise Architect.
Reviewing System Requirements related to SW scope written by System Engineers via IBM Doors.
Analysis of Hardware to Software Interface document, and creation of related High Level Design Objects/Requirement to ensure traceability.
Participating in bi-weekly Sprint Planning meetings along with SW project leader, software teams in India, Ireland and China to discuss effort estimations and assignation per team for each upcoming sprint.
Responsible for technical coaching and code reviews of India Team, consisting of 3 SW engineers.
Providing pre-commit code reviews for both India and Egypt teams, to ensure code quality as per internal development guidelines, ensure updates of SW Requirements, and High-Level Design Requirements to comply with Commit Control Board process.
Conducting technical training for China team in Cairo site, consisting of 2 SW Engineers.

3. R&D : Low-Cost Software Platform Project
Title: Embedded Software Engineer
Cairo, Egypt
Main Activities:
Reverse engineering of legacy Volvo PAC360 Surrounding View System. Legacy tools have been used as references for designing the new platform.
Design, implementation of DSP Handler SW module (DSPH), lying on top of stack of SPI, IPC layers. DSPH has been used as a generic way to interface MCUs with DSP cores.
Run PC-Lint static analysis tool for DSPH module and ensure compatibility with MISRA-C guidelines.
Providing full documentation, design and requirements specifications for the DSPH module via IBM DOORS.
Designing the modules internals using Enterprise Architect.
Attending technical meetings and workshops to interface with other module owners.
Noticeable contribution to the final form of the platform.


4. Jaguar Land Rover Rear View Camera System
Title: Junior Embedded Software Engineer
Cairo, Egypt
Main Activities:
Full design and implementation of HMI Touch Screen driver. The driver allowed the ECU to communicate with the vehicle touch screen via CAN.
Design and implementation of VDC (Video Display Control) SW module.
Full implementation of AppM module (Application Manager), a centralized point to drive SW modules lying in the Application Layer.
Bug fixing and debugging using Microchip In-Circuit Debugger for dsPIC microcontrollers.
Performance measurements, release tests, and integration testing on project horizontal scope; diagnostics, and view switching, using Agilent Oscilloscopes.
Participation in daily 5-minutes meetings, bi-weekly sprint planning inter-call meetings, and Daily Commit Reviews with Ireland team.
Ownership and maintenance of Software Requirements Specification and High Level Design documents on DOORS.
Highest number of commits into the project repository.
Achieved ASPICE Level 2 with the team

Wirtschaftsingenieurwesen