Project Manager Semiconductors, IPMA

5/2020 – 12/2020

FPGA-based systems concept, architecture, design, and verification.
Project management: scope and schedule elaboration, specification capture, release planning, milestones release, risks assessment and mitigation plan preparation.
FPGA design training: course development (XILINX (AMD), Lattice) and delivery.

Embedded Systems, FPGA, Hardware-Design, Hardwarebeschreibungssprache, Vivado (Xilinx), Projekt-Dokumentation, Projekt-Konfigurationsmanagement, Projekt-Qualitätssicherung

9/2015 – 4/2020

Managed 30+ high-security product certifications (Common Criteria, EMVCo, CUP).
Coordinated international development teams. Planned deliveries and developed certification documentation.
Planned, organized and moderated technical design reviews and audits (TÜV, Brightsight, CFNRA).
Developed communication with external certification authorities (BSI). Achieved fast and effective information exchange between subteams and customers.

Kommunikation (allg.), Picmicro, Projektmanagement (IT), Team Building, Vorbereitung auf QM-Zertifizierung (ISO)

7/2006 – 8/2015

Architected high-security Chip-card SLE78 and SLE90 microcontrollers family.
Digital design of multi-clock interface management and digital power control subsystems.
Milestone delivery planning and enabling.
Chip top-level integration, change- and configuration-management.
Design sign-off coordination.
Product security certification (Common Criteria) support.

Hardware-Design, Mentor Graphics, Verilog, Hardwarebeschreibungssprache, System Analyse, System Architektur, System Design, Team Building, Picmicro

5/2003 – 6/2006

Development of architecture and concept of ultrafast video capturing systems.
FPGA design team leadership.
System architecture design.
EDA tools park supervision and development.
Communication and customers requirements capture.

FPGA, Hardware-Design, Mentor Graphics, Hardwarebeschreibungssprache, Projektleitung / Teamleitung (IT), System Analyse, System Architektur, System Design, Team Building

9/2000 – 4/2003

Deployed bus functional models for OIF SPI-4.2, Utopia Level 3, CSIX interfaces for Q192 ASIC.
Maintained functional regression at module and system levels.
Architected Synopsys VERA-HVL verification environment and behavioral models.
Designed RTL sub-hierarchy and proprietary high-speed ASIC bus interface.
Authored technical documentation of Q192 and OC48 ASIC projects.

Mentor Graphics, Verilog, Hardwarebeschreibungssprache, Systems Simulation, CAD (computer-aided design)

9/1997 – 8/2000

Developed and delivered course lectures and labs on digital design, ASIC testing, FPGA design and verification.
Supervised R&D projects and co-operation activities under EUROCHIP/EUROPRACTICE frame-
work

Altera (allg.), Hardware-Design, Mentor Graphics, Hardwarebeschreibungssprache, Xilinx (allg.), Automatisierungstechnik (allg.), CAD (computer-aided design)