Senior embeded designer

3/2022 – offen

• Engineered a custom image processing pipeline, resulting in a 40% reduction in image processing time.
• Developed SoC system, resulting in a 30% reduction in overall system costs.
• Conducted regular consultations with 5 junior engineers, sharing expertise on FPGA design best practices, facilitated successful completion of complex projects ahead of schedule.

Digitaler Signalprozessor (DSP), FPGA

4/2019 – 3/2022

• Led a team of 3 engineers in developing a video processing system
• Crafted a real-time image processing system resulting in a 100% improvement in data throughput due to enhanced algorithm efficiency on the FPGA platform.
• Enhanced system capabilities by expanding the number of video patterns generated from 10 to 112, resulting in a 65% reduction in DSP48 utilization and a minimal increase of only ten block RAMs.
• Designed and implemented a video anti-aliasing filter, resulting in an increase in the output video quality by 2.3dB (PSNR).
• Integrated 4 complex algorithms into Xilinx Kintex UltraScale FPGA platform and optimized system design, leading to a 20% reduction in area and a 15% decrease in power utilization.
• Engaged with 28 members across 3 cross-functional departments, ensuring a 100% successful project integration.
• Uncovered and resolved critical design flaws within digital HW components, leveraging industry-standard tools and methodologies, resulting in a 30% increase in system stability.

FPGA, C++, Signalverarbeitung

9/2017 – 4/2019

• Introduced an FPGA-to-FPGA bus system, resulting in 4 times increase in data bandwidth.
• Optimized an RF receiver block, resulting in a 35% reduction in resource utilization.

Digitaler Signalprozessor (DSP), Embedded Systems, FPGA, C++, Signalverarbeitung