R&D Specialist Digital Signal Processing Critical Embedded RTOS FPGA SoC Systems

2/2017 – 8/2022

Model Based Design with MATLAB/Simulink and Xilinx System Generator of Measurement IP Core and
Patented IP Cores
RF Signal Modulation/Demodulation, Power/Phase Processing
Multi Stage FIR Filter Design with Control Logic, Dual Port RAM and DSP48 Slice
VHDL Code Generation with Xilinx System Generator DSP Builder
Simulation/Performance Tests and Optimization
Definition and Implementation of VHDL 93 Guidelines
RTL Design and Coding in VHDL 93 of RF Continuous Wave and Pulse Signals
UART Port Configuration in ANSI C
RTL Design and Coding in VHDL 93 of UART Communication PL PS UART with AXI4 Lite Protocol
Model Based Simulation with MATLAB/Simulink, Test and Optimization of the RF Power Control IP Core
ANSI C Code Porting, RTL Analysis, Synthesis and Export in VHDL 93 with Vivado HLS of the RF Power
Control IP Core
Automated Simulation Test Benches for standard protocols (SPI, I2C) with UVVM, OSVVM and ModelSim
Test Bench Simulation of generated IP Cores and VHDL Components
Studies of Xilinx Architecture Configuration, Top Level Design, Timing and IO Design Constraints, IP
Cores and VHDL Components Integration, Synthesis and Functional Verification
Phase Locked Loop Design and Analysis
Creation and Development in Python of a fully integrated RF signal analysis library
Complete restructuring of the deprecated Pico SDK Python libraries for the PicoScope 3000/5000 Series
Oscilloscopes with full functional recovery of analog and digital channel control
Rigol DG4102 RF Signal Generator Python wrapper library tests
DOE, AOE, Simulation/HIL/ATE/DVT Tests and Measurements with Python Scripts/Notebooks, Robot
Framework and PyTest
Tests and studies of ADC, DAC, JESD204B, Lock-in Amplifiers
HIL System Tests with PicoScope and Rohde & Schwarz Oscilloscopes, Rigol and Rohde & Schwarz RF
Signal Generators
Software Configuration Management with GitLab/Git Extensions
Continuous Integration and Delivery with Jenkins

Embedded Entwicklung / hardwarenahe Entwicklung, FPGA, Hardwarebeschreibungssprache