ASIC/FPGA Engineer
- Verfügbarkeit einsehen
- 0 Referenzen
- 50€/Stunde
- 70567 Stuttgart
- auf Anfrage
- hi
- 12.01.2023
Kurzvorstellung
working experience in the semiconductor industry. I am highly skilled FPGA/ASIC design & verification.
Looking for part-time work (20 ~ 25 Hours/week)
Qualifikationen
Projekt‐ & Berufserfahrung
11/2022 – offen
Tätigkeitsbeschreibung
FPGA design for Machine Vision Cameras
Design Verification
RTL Design
Device driver development
C++, FPGA, Python, Hardwarebeschreibungssprache
5/2022 – 11/2022
Tätigkeitsbeschreibung
RTL Design & (PCIe) IP integration
RTL Connectivity Verification using Jaspergold
CDC Verification
FPGA, Tool Command Language, Verilog, Hardwarebeschreibungssprache
1/2021 – 5/2022
Tätigkeitsbeschreibung
●Prototyping ASIC RTL design (Smart NIC) to FPGA (Xilinx, U280 card) .
● Writing IP wrappers, and interface adapters (native to industry standard AXI) for
IP integration.
● Synthesis, timing closure, and bitstream generation of complex designs.
● RTL simulation and debugging, including test development and writing test
benches.
● On-chip debugging using integrated logic analyzers.
● FPGA-based PCIe design (PCIe DMA, Dynamic Partial Reconfiguration of FPGA
through PCIe).
FPGA, Verilog, Vivado (Xilinx)
1/2019 – 12/2020
Tätigkeitsbeschreibung
●FPGA-based Micro-architecture design of video processing system from scratch.
● Developed image processing IP core using Xilinx High-level synthesis tool.
● Integrated Xilinx-based deep learning processing core into the design.
● Develop linux device drivers for host-fpga communication
FPGA, Verilog, Hardwarebeschreibungssprache, Vivado (Xilinx)
Ausbildung
China
Über mich
Weitere Kenntnisse
Southeast University,
China
Persönliche Daten
- Hindi (Muttersprache)
- Europäische Union
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