FPGA Design Engineer

10/2018 – 4/2020

Involved in the design of a 5G RAN testbed FPGA based board, interfacing baseband with next
generation 5G remote radio units across CPRI interfaces.
• Bringing up GTY transceivers on Xilinx Virtex Ultrascale+ FPGAs, each connecting to QSFP+28s running at 24.3Gbps per lane.
• Deframing of CPRI O&M messages and I/Q sample data and I/Q data formatting.
• Implementation of OAM control message processing modules on Ultrascale+.
Involved in the design of a 39GHz UE. Responsible for the implementation of the IF and RF board’s control functions implemented on 2 Intel MAX10 FPGAs, such as IF and RF attenuation, TX output power control.
Implementation of test GUI SW using CSharp Microsoft Visual studio.

Telekommunikation / Netzwerke (allg.)

10/2017 – 10/2018

Development of high performance modular network appliance:
Involved in the FPGA design and verification of the inline and capture cards at 10/40/100Gbps line speeds. Implemented features such as flow aware packet correlation Aurora cell access formatting and decoding.
Verification of design modules using Systemverilog and UVM.

Telekommunikation / Netzwerke (allg.)

1/2012 – 10/2017

Development of an 8 channel x 10Gb Ethernet mobile network (GPRS) traffic processing card as part of a mobile network probing system across Gn and LTE interfaces, implemented using a Xilinx Virtex-6 FPGA including embedded SW running on a microblaze subsystem as part of the FPGA.
Mainly responsible for the FPGA development: High speed serial interfaces using 10Gigabit GTH transceivers, definition of clocking architectures, implementation of digital hardware packet processing blocks in VHDL & Verilog such as IP reassembly, time-stamping, packet classification, GTP correlation, load balancing and replication across the 8 channels, interfacing with the Microblaze subsystem.
Development of the embedded Microblaze subsystem, including the development of monitoring and control software in C.
o Porting of the above processing card to a 320Gbps system using a Virtex-7 FPGA, utilizing 32 GTH transceivers on both ingress and egress interfacing with stacked QSFP+ modules (breakout to SFP+)
o Re-development of the 10G firmware to be able to process 40Gbps traffic feeds on the QSFP+ ports. Integration of the Xilinx 40GEMAC/PCS core, redesign processing blocks for a 40Gbps datapath.
o Implementation of stateful GTP correlation and load balancing on FPGA hardware, IMSI filtering, Gn/LTE filtering

Telekommunikation / Netzwerke (allg.)