FPGA/ASIC-Engineer

Almost 20 years of experience with FPGAs. Quick to deliver working Verilog/VHDL RTL. Self starter, able to do complete E2E flow from requirements, arch, design through implementation and HW testing. 5 year experience working in Germany before.

• Digitaler Signalprozessor (DSP)
• FPGA
• Hardwarebeschreibungssprache
• Python
• Simulink
• Verilog

Experienced FPGA Engineer looking for remote freelance projects on contract basis.

Verilog/VHDL RTL design
DSP algorithms, RF signal processing,channel filters, DUC/DDC
timing closure/simulation

Only remote work.

C/C++ Matlab modelling of fixed point DSP algos
some HLS Catapult
Altera/Xilinx FPGAs
ASIC design experience (frontend)
Python (testing)