FPGA SoC Designer

6/2020 – offen

Implementing algorithms on FPGA using HDL and HLS flow for L1 Trigger system of CMS. Trying to reduce latency and implementable complexity (Rent exponent). Making the designs more aligned in both HDL and HLS.

FPGA

11/2017 – 5/2020

Designed and optimized the baseband modules of 5G receiver.
Specifically, designing reference signal generation blocks, timing and frequency offset estimation, Phase noise correction blocks.
Optimizing the blocks for Intel Stratix FPGA using better routing and exploring DSP or hardware resources. Invovled in high level integration of the subsystem blocks and making the design more programable.
Also, involved in designing hardware accelerators for the 5G receivers modules and integrating the functionality with the RISC-V based control core.

Digitaler Signalprozessor (DSP), FPGA, Telekommunikation / Netzwerke (allg.)

12/2016 – 9/2017

Developed a real time test bed receiver based on Xilinx FPGA to test low energy modulation schemes, specifically OOK design. In this thesis, I explored various aspects of digital design of blocks such as timing analysis, floor plan, impact of operational bits etc. Also, tested the performance of system under a wide band ADC, utilizing its full dynamic range.

Digitaler Signalprozessor (DSP), FPGA, Simulink, Telekommunikation / Netzwerke (allg.)