FPGA Entwicklung (DO-254)

7/2013 – 5/2016

C919 Cockpit Display System Project:
- DO 254 certification support.
- Requirements capture for the Mixer and Monitor FPGAs.
- Implementation of the Head Up Display (HUD) logic in the Mixer FPGA (IGLOO2,
* Reverse calculation of the alpha channel from the GPU video input.
* Real time bore-sighting of the Enhanced Video System (EVS) video input
* Real time scaling of the EVS video input using a bilinear algorithm.
* Real time brightness an d contrast adjustment of the EVS video input.
* Merging the GPU and the modified EVS video streams using alpha blending.

C919 AFDX Switch Project:
- DO-254 certification support.

FPGA, Hardwarebeschreibungssprache, Raumfahrttechnik

6/2012 – 2/2014

Feasibility study Fly by wire avionic systems for a helicopter:
- Definition of the hardware architecture to satisfy the customer requirements in terms of processing power, I/O capabilities, power dissipation, size, environmental, etc. for:
* the Central Processing Modules (CPM)
* the I/O Modules (IOM)
* the Actuator Control Modules (ACM for main and tail rotors)

Research Project - CPU Board for a dual lane Remote Control Electronics
- Schematic capture of the Central Processing Unit (MPC8349A, PCI, DDR2, Gbit Ethernet,
USB 2.0, ProASIC3, Stratix II, Flash, NVRAM, AFDX, CAN, ARINC 429, RS 232)
- Integration of all the modules to create the board schematic (PSU, CPU, DSP and I/ O).
- Constraining the PCB to ensure reliable operation (Cadence’s Allegro Design Entry HDL, SigExplorer)
- Perform ing the Signal Integrity analysis for the high speed and high load buses (DDR2, PCI, SigExplorer)
- Design of the Serial to Parallel (S2P) FPGA to interface the I/O with the CPU
* Requirements capture for the FPGA.
* Design and implementation of the FPGA (Microsemi ProASIC3, VHDL, Synplify)
* Performing the simulation (writing the tes t bench and simulation models) using ModelSim to verify the design.

FPGA, Hardware-Design, Hardwarebeschreibungssprache, Raumfahrttechnik

4/2010 – 12/2014

Development of DO-254 IP Cores (DAL A) in VHDL:
- Development of IP Cores to DAL A according to the DO 254.
* MIL-STD-1553B
* CAN
* Ethernet (10/100/1000 Mbps)
* ARINC 429
* SDRAM Controller ; and more
- Requirements capture for FPGAs according to the DO 254 (DAL A) for several clients.
- Test specification definition for FPGAs according to the DO 254 (DAL A) for several clients.
- Development of test benches to verify FPGAs according to the DO 254 (DAL A) for several clients.
- Performing independent reviews on different design data (requirements, test specifications, FPGAs source code, etc.) according to the DO 254 (DAL A) for several clients.
- Support during the EASA certification audit (SOI#2 and SOI#3) for a product including the CAN IP Core.

FPGA, Hardwarebeschreibungssprache, Raumfahrttechnik

4/2008 – 3/2010

Common Remote Data Concentrator (cRDC) for the A350 IMA Project:
- Suppor t during the EASA certification audits (SOI#2 and SOI#3).
- Support during Airbus audits (SOI preparation and CFAR)
- CPU Core:
* Requirements capture for the Central Processing Unit of the CRDC (MPC8349A, DDR2, ProASIC3, Stratix II, Flash, NVRAM, AFDX)
* Schema tic capture and PCB constrain s definition (Cadence’s Allegro Design Entry HDL, SigExplorer)
* Perform ing the Signal Integrity analysis for the high speed and high load buses (DDR2, PCI, SigExplorer)
* Software revision and help in integration to ensure correctness when accessing the hardware.
* Writing the documentation of all the stages of the process in accordance to the DO-254 Standard (DAL A) and the internal Quality Process.

- CAN/A429 ASIC:
* Requirements capture for the FPGA/ASIC (CAN, ARINC429, DOORS).
* Designing and implementation of the FPGA (Altera Stratix II, VHDL, QuartusII)
* Performing the Static Timing Analysis (Timing Designer, TimeQuest).
* Writing the documentation of all the stages of the process in accordance to the DO-254 Standard (DAL A) and the internal Quality Process.
* Prepare the reviews with Altera for the HardCopy design.

- S2P FPGA:
* Requirements capture for the FPGA (DOORS).
* Designing and implementation of the FPGA (ProASIC3, VHDL)
* Performing the Static Timing Analysis.
* Writing the documentation of all the stages of the process in accordance to the DO-254 Standard (DAL A) and the internal Quality Process.

- Mockup Miniboard:
* Requirements capture for a prototype board to test the system concept and
architecture containing a DSP and an FPGA (TMS3 20F2808, ProA SIC 3)
* Schematic entry and PCB constrain (Cadence’s Allegro Design Entry HDL,
SigExplorer)

FPGA, Hardware-Design, Hardwarebeschreibungssprache, Raumfahrttechnik

10/2007 – 4/2008

Program and Technology details omitted as per client's request:
- Requirements capture for an FPGA included in a Primary Flight Control Unit.
- PCBs Signal Integrity study and improvements
- Design and implementation of the FPGA to DAL C
- Performing the Static Timing Analysis.
- Performing the simulation (writing the test bench and simulation models) to verify a different FPGA (DAL A).
- Writing the documentation of all the stages of the process in accordance to the DO-254 Standard (DAL A/DAL C) and the internal Quality Process.
- Support during the EASA certification audits (SOI#1, SOI#2, SOI#3 and SOI#4).

FPGA, Hardware-Design, Hardwarebeschreibungssprache, Raumfahrttechnik

4/2007 – 9/2007

- Requirements capture for the Data Output FPGA (DOORS).
- Design and implementation of the Data Output FPGA (ACTEL Pro ASIC 3, VHDL, Synplify)
- Static Timing Analysis of the design (Timing Designer,
- Performing the simulation (writing the test bench and simulation models) using ModelSim/Cadence NC VHDL to verify the Frame Grabber FPGA
- Writing the documentation of all the stages of the process in accordance to the DO-254 Standard ( DAL A) and the internal Quality Process.

FPGA, Hardwarebeschreibungssprache, Raumfahrttechnik

11/2006 – 4/2007

AFDX Project:
- Writing the System Specifications of an FPGA to perform some of the AFDX (ARINC 664) related functions and its interface to an MPC5554.

ERIU Project:
- Writing the Specification and Requirements for the Engine Rating Interface Unit.
- Design and implementation of the FPGA and test benches (VHDL, Visual Elite, ModelSim, ISE, Cadence NC VHDL Simulator).
- Design of a Test Box to verify the product (Schematic entry).
- Writing the documentation of all the stages of the process in accordance with company standards and methodologies.

FPGA, Hardware-Design, Hardwarebeschreibungssprache, Raumfahrttechnik

9/2005 – 3/2007

- Requirements capture for the Enhanced Vibration Processing Unit (eVPU) FPGA (Reqtify).
- Design and implementation of the (DAL B) FPGA (Xilinx Spartan3, VHDL, Visual Elite, Synplify)
- Static Timing Analysis and simulation (ModelS im/Cadence NC VHDL).
- Schematic design of the digital circuitry: DSP, FPGA, D/A, A/D, SDRAM, DDRAM, etc. (Cadence’s Allegro Design Entry HDL)
- Signal Integrity study of the PCB DDR & SDRAM interfaces and re designed them to improve performance (Cadence's SpectraQuest).
- Design of automatic on board tests (JTAG, assembly and C) for the PowerPC5200B and the TI C6713 DSP to ease prototype debugging and industrialization process.
- Design and implementation of an acquisition software on the TMS320C6713 SDK to test the suitability of t he A/D converters (ADS1271).
- Software revision and help in integration.
- Writing the documentation of all the stages of the process in accordance to the DO-254 Standard (DAL B) and the internal Quality Process.

FPGA, Hardware-Design, Hardwarebeschreibungssprache, Raumfahrttechnik

7/2005 – 8/2005

Definition of the technical solutions for a new product used to automatically recognize shape and drills in glasses using scanners technology and image processing.

Embedded Entwicklung / hardwarenahe Entwicklung

10/2004 – 7/2005

Analysis of the NH90 NAHEMA SMS Release Controls and Safety Interlocks FPGAs to verify engineering requirements and specifications.
- Writing the documentation for the existing VHDL code
- Coding a Test Bench to cover/simulate the FPGA requirements.
- Fixing bugs
Boards modification to be compliant to the new client requirements (NH90 NORDIC)
- Specification of the new requirements
- Coding and integrating the new VHDL functionalities.
- Coding a Test Bench to cover/simulate the FPGA
- Re-design of the test rig (schematic, VHDL and control software) to allow testing the old and new boards and to add some new capabilities (scripting language)
- Writing scripts to test all the electronic on board.
- Documenting all the stages of the process in accordance with company standards and methodologies ( DAL B).
- Design and implementation of a StingRay torpedo and a Marte MK2 Anti Ship
Missile simulators.
- VHDL code
- C++ code to create an interactive windows interface

Hardware-Design, Hardwarebeschreibungssprache

10/2004 – 7/2005

Analysis of the NH90 NAHEMA SMS Release Controls and Safety Interlocks FPGAs to verify engineering requirements and specifications.
- Writing the documentation for the existing VHDL code
- Coding a Test Bench to cover/simulate the FPGA requirements.
- Fixing bugs
Boards modification to be compliant to the new client requirements (NH90 NORDIC)
- Specification of the new requirements
- Coding and integrating the new VHDL functionalities.
- Coding a Test Bench to cover/simulate the FPGA
- Re-design of the test rig (schematic, VHDL and control software) to allow testing the old and new boards and to add some new capabilities (scripting language)
- Writing scripts to test all the electronic on board.
- Documenting all the stages of the process in accordance with company standards and methodologies ( DAL B).
- Design and implementation of a StingRay torpedo and a Marte MK2 Anti Ship
Missile simulators.
- VHDL code
- C++ code to create an interactive windows interface

FPGA, Hardware-Design, Hardwarebeschreibungssprache, Raumfahrttechnik

6/2002 – 10/2004

Aermacchi M-346 Project:
Re-Design of the Central Processing Unit (CPU) and Input Output Controller (IOC) boards for
the M346 Aircraft's Flight Control Computer (FCC).
- VHDL coding of the safety critical (DAL A) FPGAs
- Test-Bench creation and simulation using ModelSim to verify the design.
- Static timing analysis.
- Schematic design.
- Design of automatic on board tests using assembly and C for the PowerPC603 microprocessor (CPU board) and the TI C6701 Digital Signal Processor (IOC board) to ease prototype debugging and industrialization process. Tests include: 1553 avionics bus, Arinc429, Cross Channel Data Link, Interrupt controller, timers, memories and any other on board device.
- Help on the software-hardware integration stages, where a good knowledge of the
existing hardware is required along with the capability of understanding the
software design and requirements.
- Documenting all the stages of the process in accordance with company standards and methodologies.

FPGA, Hardware-Design, Hardwarebeschreibungssprache, Raumfahrttechnik