FPGA and Embedded Software Design Engineer

11/2017 – 4/2018

Equine ultrasound probe
● Beamformer RTL IP repurpose for higher resolution and smaller depth
● Product IDs functionality addition in firmware

Easi-Scan Go
● Beamformer RTL IP design
● Altera Cyclone V ARM Linux kernel compilation flow development
● Device tree source development
● Filesystem compilation flow development
● Boot image development
● Firmware design

Embedded Linux, FPGA, Verilog, Firmware

9/2017 – 10/2017

● Firmware development for the implementation of MD5-hash based verification of product registration.
● Firmware development for the implementation of balanced use of the nitrogen generator sub-compartments.

Firmware

9/2017 – 10/2017

● Study and implementation specification of a High-Level-Data-Link (HDLC) MAC and LLC engine.
● Implementation of the HDLC firmware component for both station and access points.
● Verification of the HDLC firmware against third party electrical meter and virtual DLMS server

Embedded Linux, HDLC (High-Level Data Link Control)

6/2017 – 6/2017

● Studied existing code and existing limitations for porting solution to Windows 10
● Proposed solution via the development of a Windows 10 printer driver installer
● Implemented Windows 10 driver installer software

Computerprogrammierung

5/2017 – 8/2017

● FPGA design from scratch of a system interfacing to 3 different peripherals, one MCU and an external memory module.
● FPGA / MCU communication verification with firmware design engineer
● FPGA design bring-up against hardware module.

FPGA, Verilog, Firmware

3/2017 – 11/2017

Subsea Electronic Module controlled via PLC over PROFINET

● PROFINET protocol study and implementation planning
● Firmware and FPGA architecture specification and development roadmap
● Firmware development for HSCAN, FTCAN, serial I2C, and SPI peripherals
● Firmware integration into FreeRTOS
● FPGA design and verification
● PLC - field device interface bring-up and GSD development

FPGA, Verilog, Hardwarebeschreibungssprache, Firmware

1/2015 – 8/2015

SPI to SDRAM Interface.
● Solution architecture specification
● Project management
● Verilog Design
● CPLD Implementation and Verification
● Creation of demo for client

SPI to SRAM Interface
● Solution architecture specification
● Project management
● Verilog Design
● CPLD Implementation and Verification
● Creation of demo for client

Mentor Graphics, Quartus (Altera), Verilog

1/2014 – 3/2017

LiFi integration in Broadcom SoC
● ASIC architecture definition
● Integration process definition
● IP buses width, bandwidth, role and end point definition
● Verification process definition
● FPGA non-synthesizable components replacement with RTL blocks

Li-Fi-X
● Cypress FX2 device USB firmware development
● RTL FIFO design for Cypress FX2
● LatticeMicro32 soft-core integration
● Complete USB to WiFi stack development on Linux driver
● Android drivers complete development and technology integration
● Embedded linux kernel customization
● Complete USB to WiFi stack development on Windows driver
● Complete USB to WiFi stack development on MacOS driver
● 802.11i encryption/decryption algorithms development
● User-space applications configuration tool development
● Verification of the final solution

Li-Flame
● LiFi RTL IP multiple access and handover functionality addition
● Soft-core firmware modification for multiple access and handover
● Linux network drivers development and kernel customization
● User-space application configuration tool development
● Windows driver development
● Verification of the final solution

10Mbps Li-Fi Connectivity Solution
● External RTL IP repurpose from WiFi to LiFi
● FPGA soft-core assembler design
● FPGA soft-core firmware design
● RTOS development on TI DSP/BIOS
● DSP filtering implementation
● Embedded lInux driver development.
● User-space applications development.
● FPGA code modification for throughput increase.
● System verification

Embedded Linux, FPGA, Verilog, Hardwarebeschreibungssprache, Vivado (Xilinx), Computerprogrammierung, OSX, Firmware

12/2012 – 12/2013

BSI 8MP camera sensor
● Port of the existing verification platform to a UVM based verification.
● Creation of IP-level UVM test-benches for other members.
● Support in UVM verification for all the members in the team.
● Merge of the analogue mixed signal flow to the UVM test-bench for higher usability.
● Embedded software design in C for sensor setup and control for 8051.
● Image compression encoding block design
● Status line controller block design
● Analogue / digital interface development
● AMS verification support
● csh scripting
● Main responsible for the sensor verification

Proximity / ALS sensor development revision 1.1
● Main verification responsible for RTL and netlist creation
● AMS verification support
● Embedded software design in custom assembly covering new functionalities

8MP camera sensor
● Analysis of the system architecture to be deployed
● AMS verification support
● UVM Verification platform creation for the complete system.
● Synthesis of blocks and checks for timing constraints.
● Blocks creation with Catapult-C
● Acquaintance of younger members with the UVM flow.

Proximity / ALS sensor development revision 1.0
● Support verification of the sensor before the tape-out.
● Python scripts for regression automation.

FPGA, Verilog

10/2010 – 12/2012

LTE Turbo Encoder / Decoder IP
● Analysis of architecture for a customizable LTE error correction unit.
● Design in Verilog.
● Design of bit-accurate model in Matlab.
● Verification was done both on FPGA and in Modelsim
● Patented low – area / power implementation of the interleaver / de-interleaver blocks.
● Linux driver development for PCI cards.
● Linux driver development and embedded software development for device USB bundle.

802.11 WLAN Decoder
● Perl script design for translation of Verilog blocks to VHDL.
● Design of AMBA bus.
● Designed blocks for FPGA in order to facilitate communication of the system with the host via USB.
● DSP processor DMA and filtering blocks implementation

DVBT Decoder
● Design of IIR filtering blocks.
● Generic FIFO
● Verification and debug of protocols on FPGA

MIMO -WLAN Decoder
● Updated signal conditional blocks for support of antenna with wider band and worse SNR.
● Fine-tuned software and hardware blocks operation in order to meet power constraints. Netlist simulations and power profiling was done with Palladium tools. Exact power measurements were done with PrimeTime PX.
● Supporting UVM team in order to resolve issues in the system.
● Designed new blocks supporting MIMO WLAN protocol.
● Working with the SystemC team in order to resolve issues in mismatch between model and RTL in our DSP., DMA and Viterbi blocks.
● Supporting verification team by providing bit-streams for multi-FPGA projects. Synthesis was done with a combination of Certify, Synplify – Pro and Xilinx ISE flow.

FPGA, Verilog, Hardwarebeschreibungssprache