Embedded, FPGA and Digital Design Engineer

10/2021 – 6/2022

ASPICE, FPGA, CyberSecurity, Polarion

FPGA

4/2020 – 3/2022

System architect and technical project leader in Railway/Medical sector.
System Architecture (IEC501xx)
RAMS, CCA, FMEDA, MTBF
FPGA Architecture

Embedded Entwicklung / hardwarenahe Entwicklung, FPGA, FMECA (Failure Mode and Effects and Criticality Analysis), System Architektur

11/2018 – 9/2019

Secure Remote Update System in kritischen Einsatzgebiete
Design of Secure and Safe Remote Update System for SIL3 application. The Remote update system consists of On-Chip Flash Memory IP and Flash Controller, DMA, FSM, Command-Processor, configurable CRC unit.
VHDL, C, Max10, Cyclone V, LVDS Communication

FPGA, Scrum, Projektmanagement

5/2018 – 12/2019

Technical and Discipline Leadership with Account Management responsibilities.
Developing ADAS Solution using Radar and Camera Systems
Artificial Intelligence and Deep Neural Networks.
CNN accelerators (VHDL implementation)
Camera Interface (xilinx IPs)
OpenVino
Revision
DNNDK
CNN
OpenPose

FPGA, Deeplearning4j, Faltendes Neuronales Netzwerk (CNN), Maschinelles Lernen, Neuronale Netze, Support Vector Machine, Projektleitung / Teamleitung (IT), Python, Kameratechnik, Radar

6/2016 – 12/2016

FPGA Design
Sensors
Antriebstechnik
Verification
SIL3

FPGA, Antriebstechnik, Sensorik

3/2015 – 5/2018

Technical Project Leader.
Projects:
1- Pedestrian recognition and tracking using OpenTLD. Implementation over Nvidia JetsonTX1 (CUDA, Python, C++)
2- Kalman-Filter for object tracking (Python, C, VHDL)
3- VHDL implementation of Image Processing Accelerators

Hardwarebeschreibungssprache, Projektleitung / Teamleitung (IT), Scrum, Python, Enterprise project management (EPM)

5/2013 – 5/2015

System Architect Medical Devices
I was responsible for developing and maintaining system architecture for Surgical Guidance Eye-Diagnostic Laser Devices. Enterprise Architect (UML). Coordination with Pre-DEvelopment Teams, Development Team and Engineering. Maintaining and assuring development according to ISO 14971:2012. Coordinating SW-Architecture, Electronic Architecture, and Mechanic Architecture.
Leading architecture status meeting.

Hardwarebeschreibungssprache, Enterprise Architect (EA), Simulink, Requirement Analyse, Iso 26262

1/2012 – 12/2012

- Developing hybrid smart systems for managing and storing PV and thermal energies in the presence of conventional fuel-burning generators.
- Responsible for leading the technical work on solutions for PV energy storage as well as load management in self-sufficient smart-homes as part of the E³ product and E-mobility Project.
- Communicate and coordinate work for Schüco with partners and technology providers.

Elektrische Energietechnik, Prozessvalidierung

6/2009 – 12/2011

ASIP/ASIC Developing Engineer, iAd GmbH, Grosshabersdorf, Germany.
iAd GmbH is a design and fabricating house for industrial automation and Power-Line Communication (PLC) targeting the emerging Smart-Grids.
- I led the efforts for analysing, designing and implementing industrial security for smart grids and the narrow band power-line communications.
- This joint effort encompasses designing the underlying security ASIPs for ciphering, key management and digital signature.
o Cryptography: cyber-security conception and implementation for the emerging power-line modems I put the security concept for secure communication over power-line modem chips using some cryptography services including authentication,
o Designing a key management, integrity and confidentiality. Cryptography Algorithms such as AES (128-, 192-, and 256-bit), ECDSA, ECDH, Key-Wrap, RSA and others have been developed and implemented on ASIC/ASIP with a thorough and solid understanding in computer arithmetic, controlling fabrics and digital design.
o Designing an ECDSA digital signature ASIP for general prime curves (ANSIx9.62), key management unit with wrapping/unwrapping protection,
o Designing an AES unified for 128-,192-,256-bit keys on several operation modes for encryption and decryption.
o The ECDSA ASIP is very competing in terms of area, performance and side-channel attack resilience
- Digital Analog Backend: concept, designed and verified a novel Low Oversampling Rate High Quality Delta-Sigma Modulation System. (Patent) The novel DSM works for wideband OFDM

Mathematik, FPGA, Hardwarebeschreibungssprache, Kryptographie

11/2004 – 12/2008

Research associate, Hamburg university of technology (TUHH), Hamburg, Germany.
I developed and implemented a complete PSoC FPGA System with 128nm Technology. The FPGA included 256 RISC CPUs, LUTs, scalelabel and Extandable DSP units, Configurable Routing Fabric...
- Reconfigurable computing interdisciplinary research efforts (processor architecture, Information theory, computer arithmetic, ASIC design, CAD tools etc.)
- Instructing Digital Signal Processors and Digital Processing Design.

Informationsdesign, Digitaler Signalprozessor (DSP), FPGA, Hardwarebeschreibungssprache, C++, Halbleiter

1/2004 – 12/2004

- Development of video coding standards for HDTV.
o VHDL/Verilog
o RTL-Design. Major: Video Coding Standards MPEG4/H264.
o C++ system modeling.

Mathematik, Verilog, Hardwarebeschreibungssprache, Videotechnik