Hardware Engineer

9/2019 – offen

Design, verification, and implementation of memory-system components
for Mali GPUs. RTL design and formal verification of power and clock
domain crossing bridges and their integration and UVM verification at
the system level. Updates and maintenance of memory-system-level
UVM testbench. Validation and enabling of Cadence iSpatial physical
synthesis flow. Patent Application: P06718 Extension of multicast
network over power domain boundaries

Verilog

10/2018 – 9/2019

Developed testbenches for RTL subsystems using UVM and adhoc (svunit)
methodologies for Intel FPGA accelerators. Followed agile principles.

Verilog

9/2018 – 9/2019

UVM verification of directory memory and protocol FSM units in a node
controller ASIC for cache-coherent scale-up systems

Verilog