M.Sc. Dipl.-Ing. Analog and Mixed-Signal Modeling and Verification Engineer

10/2016 – 7/2017

AMS Modeling and Verification Engineer

Verilog

8/2016 – 10/2016

AMS Modeling and Verification Engineer

Verilog

3/2015 – 8/2016

ADPLL Digital Radio SXM Tuner Project, 4.3GHz.
- Responsible for the creation and maintenance of the self-checking AMS RF behavioral models involved in the design along with their verification and validation against schematic and spec
- Executing Top-Level AMS simulation and verification using a makefile based on irun, assertions (sva and psl), monitors, checkers and the self-checking Verilog-AMS wreal models
- Running Connectivity Checks using amsDmv PinCheck to compare the module interface and pin declarations of the wreal models against the reference design (schematic, symbol and layout)
- Using irun and amsDmv to create fully digital regression simulation scripts and reports
- Modeling Design for Testability behavior (DFT) to be used in top-level verification
- Using Verilog-AMS Real Number approach (wreal) to model following blocks:
SBAND Tuner, Low Noise and Transimpedance Amplifiers (LNA and TIA), Quadrature Signal Generator, I and Q Mixers, 1st order LPF, Slew Rate Control, Clippers, Level Detectors, Wide Band Dual ADC, 4th order Sigma Delta Modulator, Cristal Oscillator with Phase Noise Jitter, Antenna Supply, Temperature Sensor with Bandgap Temperature Curve, Shielded Lines, Low Dropout Regulators, Low Frequency Divider, Voltage and Bias Current Generator, ATB MUX
- Deciding which functionality is relevant for top level functional verification and implementing the models accordingly keeping in mind the trend-off between speed and accuracy
- Running top transistor-level simulation and migrating to a Mixed-Signal simulation flow by replacing key blocks with their respective models to speed up the performance
- Running IP transistor-level simulation e.g. SBAND Tuner to investigate the deviation with respect to the IC Specification Document
- Using advanced DSP and RF theory concepts for creation of the models and the top level simulation: sampling with 4 times the maximum input frequency to achieve a fast simulation while avoiding aliasing effects (Nyquist). This applies for all the blocks.
- Using the Bilinear Transformation to convert the continuous transfer function (s-domain, laplace transform) of a Low Pass Filter with specific characteristics in a discrete transfer function (z-domain) and using warping to reduce and compensate the effects of aliasing as the input approaches the Nyquist frequency
- Using ViVA to plot the Spectrum (Discrete Fourier Transform, Hamming Window) of the LPF output when a sum of sinusoidal signals is applied to the input in order to obtain the Bode Diagram of the phase and magnitude
- Converting complex 4th order Sigma Delta Modulator’s matlab model into Verilog-AMS (wreal)
- Using matlab post-processing to compare Verilog-AMS and Matlab Model’s response by analyzing the Noise Quantization Spectrum
- Using SMG (Schematic Model Generator) to support and automate the creation of models
- Using AMS Designer, ADE-XL, irun, schematic testbench, Hierarchy Editor and amsDmv (Analog Mixed-Signal Design Model Validate) to validate the behavioral model against the transistor-level design in an mixed-signal environment as well as creating amsDmv regression simulations
- Customizing Connect Rules for Mixed-Signal simulation (adjusting vsup, vdelta, vtol, currentmode for current ports, idelta, itol, input and output impedances, rise and fall time, etc)
- Using Interface Element/IE-card based setup (OSS/UNL) to customize the Connect Modules
- Creating an executable script .sh to synchronize models located in coReuse and OA databases
- Creating AMS Model Specification documents in DOORs using the IC Design Specification and the transistor-level design (schematic) as a reference
- Creating Model Sign-Off documentation which includes “AMS Model versus AMS Model Specification” and “AMS Model versus Schematic” validation based on fully digital and mixed-signal simulation results obtained from regression scripts

Elektronische Schaltungstechnik

3/2013 – 3/2015

Consultant at NXP, Hamburg
IC for Smart Card Application; Top Level Analog and Mixed-Signal Verification and adaptation of a VBA Script for automation of the process i.e. automatic creation of stimulis using a generic testbench and analysis of simulations results and measurements according to V&V Plan, Analog Top Level extracted simulations, Review of digital std libraries for their utilization in an AMS Environment, OCEAN SKILL Scripting, ams modelling

Elektronische Schaltungstechnik

3/2012 – 3/2013

Consulting on Customer’s site (NXP, Hamburg):
IC for Smart Card Application; Top Level Analog and Mixed-Signal Verification, verilog-A Behavioral Modelling of key blocks to speed up simulations, Test Chip Simulation, OCEAN SKILL Scripting, Definition and Elaboration of Testbenches, Elaboration of Integration and Validation Plans and Technical Documentation

Elektronische Schaltungstechnik

2/2011 – 3/2012

TES Electronic Solutions,
Turn Key Customer Project (ATMEL, Heilbronn):
Analog IC Design and Layout for Can Bus Transceiver (oscillator, bandgap and
bias generator, voltage regulator, power-on reset) in a proprietary 150nm HVCMOS/
SOI process; System Design Implementation.
Development of Verilog-A models for top level and system verification.

2/2010 – 2/2011

TES Electronic Solutions,
Internal Project
IP Development

3/2009 – 2/2010

TES Electronic Solutions,
Turn Key Customer Project (LFoundry):
Analog Block Design and Layout for Ultra Low Power ?C ASIC, LFoundry 150nm
CMOS process.

2/2008 – 2/2009

TES Electronic Solutions,
Consulting on Customer?s site (Texas Instruments, Freising):
Block Circuit Layout in Portable Power Management Application, (Cadence, Virtuoso,
Assura). TI 0.35? BICMOS process.

9/2007 – 2/2008

TES Electronic Solutions,
Mixed Signal Custom Turn Key Project (Texas Instruments, Freising):
Block Circuit Design, Verification and Layout in RFID Application, (Cadence
Spectre, Virtuoso, Assura). UMC 0.35? Embedded EEPROM CMOS process.

4/2007 – 9/2007

TES Electronic Solutions,
Consulting on Customers site (Texas Instruments, Freising):
Design Changes, Verification and Modelling of Level Shifters (Cadence Spectre
VerilogA). TSMC 0.18? CMOS process.

11/2006 – 4/2007

TES Electronic Solutions,
Consulting on Customers site (Texas Instruments, Freising):
Design Changes, AMS Verification and Modelling of Digital Controllable Oscillator
(Cadence Spectre, Ultrasim, cadence AMS, VerilogA).
TSMC 0.18? CMOS process.

9/2006 – 11/2006

TES Electronic Solutions, Custom project :
Block Layout of RF Circuits (TSMC 90nm RFCMOS)

11/2005 – 4/2006

Study oriented internship at Atmel Germany GmbH, Heilbronn
Mixed-Signal Modelling (Verilog-AMS) of a Power Management System for a LF-3D
Receiver of a Passive Keyless Entry (PKE) system

3/2005 – 11/2006

Master Thesis at Atmel Germany GmbH, Heilbronn:
Verilog-AMS modelling of a Mixed-Signal IC (12/24V Power Supply) and a modular
testbench

3/2004 – 3/2005

Institute Entwurf Integrierter Schaltkreise at Hochschule Mannheim
Hardware Modelling of Digital Systems and Testbenches in VHDL (Student
Assistant)

3/2003 – 3/2004

Institute Analogtechnik at Hochschule Mannheim
Measurement and Build-up of Electronic Analog Circuits (Student Assistant)

9/2002 – 2/2003

Costa Rican Institute for Electro-Technology
Study oriented internship in Fibre-Optics Department

3/2002 – 9/2002

Bachelor Thesis at University of Costa Rica
Installation of a robotic arm Stäubli RX 90 CR and programming of a control
Routine in V+